What Every New Engineer Should Know About PCB Materials
TL;DR – PCB materials, fast:
Start with your toughest constraint – signal loss, temperature cycling, bend radius, or budget – and let that determine the material family. Use FR-4 for general applications and shorter links. Choose low-loss epoxy or PTFE/hydrocarbon-ceramic laminates for high-speed (10–28+ Gbps) and RF designs. Select polyimide when high temperatures or flex performance are required.
For signal integrity, prioritize a low dissipation factor (Df), specify HVLP or rolled-annealed (RA) copper, and use spread glass to reduce skew while maintaining consistent dielectric constant (Dk).
For assembly reliability, target a glass transition temperature (Tg) of at least 170 °C, confirm decomposition temperature (Td) against expected reflow cycles, and require low Z-axis coefficient of thermal expansion (CTE).
Lock in dielectric thicknesses early and prototype using the intended production stack-up. Source materials to a defined performance window – Dk/Df, Tg/Td, Z-axis CTE, and copper foil roughness – with approved equivalents to protect against supply chain disruptions.
If you’re taping out your first board, choosing the right laminate can feel like alphabet soup. This PCB materials guide breaks down the essentials – what properties matter, the trade-offs between common material families, and a practical pathway to the right choice for your stack-up and budget. For deeper selection frameworks, see our August piece, PCB Materials: How to Choose What Works for Your Design, which expands the decision tree for cost, performance, and lead time.
The Signals Beneath the Acronyms
When engineers talk about materials, two electrical properties dominate early conversations: dielectric constant (Dk) and loss tangent (Df). Dk tells you how much the material slows signals and therefore influences impedance and geometry; lower Dk supports slightly smaller impedance-controlled traces at a given target. Df quantifies how much signal energy turns into heat as waves propagate; lower Df is essential as you move into higher data rates or RF.
Thermal limits matter just as much in practice: Tg (glass transition) marks where resin softens, Td (decomposition) is where chemistry begins to break down, and Z-axis CTE controls how much the stack expands through its thickness – critical for via reliability across multiple lead-free reflows. Finally, copper and glass are not passive bystanders: foil roughness (ED vs. HVLP/RA) can be a first-order term in insertion loss at high frequency, and glass weave choice influences skew on fast differential pairs.
Quick Glossary (you’ll see these everywhere):
- Dk (εr, dielectric constant): How much the material slows signals; lower Dk = faster propagation, smaller impedance-controlled geometries.
- Df (loss tangent): How much signal energy turns into heat; lower Df is better for high-speed and RF.
- Tg (glass transition): Temperature where resin softens; higher Tg improves thermal robustness.
- Td (decomposition temp): Where resin chemically breaks down; higher is safer for multiple lead-free reflows.
- CTE (coefficient of thermal expansion): Expansion with temperature; Z-axis CTE drives via reliability.
- Prepreg/Core: Glass-reinforced resin sheets (prepreg) and cured laminate plates (cores) used to build the stack-up.
- ED vs. RA copper: Electro-deposited (standard, rougher) vs. rolled-annealed (smoother, better for high speed/flex).
The Core Considerations for Material Selection
1) Signal Integrity: Dk, Df, and Copper Roughness
For high-speed digital, SerDes, or RF, Df is the first filter. Standard FR-4 can work into the low multi-Gbps range on short runs, but for longer links or mmWave, you’ll want low-loss or very-low-loss resin systems and smoother copper (e.g., HVLP/RA). Dk consistency matters for impedance control; mixed glass styles and resin content create skew if you push the edge.
Rule of thumb:
- Up to ~5–10 Gbps, short runs: high-Tg FR-4 or low-loss FR-4 variants.
- Above ~10–28+ Gbps or RF front ends: low-loss PTFE/hydrocarbon/ceramic systems and smoother copper.
Planning layers and dielectrics early prevents avoidable ECOs—our Stackup Strategy guide (link below) walks through pre-fab checks that keep impedance on target.
2) Thermal & Reliability: Tg, Td, and Z-axis CTE
Lead-free assembly, thick copper pours, and multiple reflows stress your stack. Choose Tg ≥ 170 °C for most modern products and check Td if you have multiple cycles or high dwell. For dense via fields (BGAs, backplanes), low Z-CTE reduces barrel cracking and pad lift.
3) Mechanical & Environment
Bend/flex zones, vibration, and temperature swings push you toward polyimide (high temp, robust) or flex laminates (PI film + RA copper). For outdoor or aerospace, consider moisture uptake, outgassing, and CAF resistance (conductive anodic filament growth).
Core considerations: signal integrity, thermal reality, mechanical environment
For high-speed serial links, SerDes channels, and RF front ends, start with Df and copper roughness. On short runs up to the low multi-Gbps range, high-Tg FR-4 often works, but longer links or mmWave typically require low- or very-low-loss resin systems and smoother copper (HVLP or RA). Consistent Dk across your stack improves impedance control; watch mixed glass styles and resin content if you’re on the edge of margins.
Thermal design is the second lever. Lead-free assembly, thicker copper pours, and multiple reflow cycles push you toward Tg ≥ 170 °C, healthy Td, and a low Z-CTE to limit barrel cracking in dense via fields.
Finally, the mechanical and environmental context will narrow choices: dynamic bend zones and repeated flexing favor polyimide-based flex laminates with RA copper; outdoor and aerospace applications bring moisture management, outgassing, and CAF resistance into the conversation.
What to use, when
FR-4 (standard to high-Tg) remains the workhorse for general digital, power, and mixed-signal designs, especially when the longest critical nets are modest. It’s ubiquitous, affordable, and well understood at most fabs, though Df and Z-CTE vary by resin system and glass style. When channels stretch or budgets tighten on insertion loss, low-loss/very-low-loss epoxies provide noticeably lower Df with similar processing, offering strong cost/performance balance; just be explicit about copper roughness on high-speed layers.
At true RF/microwave/mmWave, PTFE and hydrocarbon-ceramic systems (the “Rogers class”) deliver stable Dk and ultra-low Df with smooth copper options, but they demand more attention to bonding, drilling, and plating, especially when mixed with FR-4. For sustained high temperature or flex/rigid-flex, polyimide shines thanks to thermal stability and mechanical endurance; treat moisture uptake and adhesive/coverlay choices as first-class design variables. Heat-dominated designs – LED lighting, power conversion, and harsh environments – often benefit from metal-core (aluminum MCPCB) or ceramic substrates (AlN, alumina), which trade density and cost for excellent thermal paths and stiffness.
Copper, glass, and the “small” details that move the needle
At higher frequencies, foil roughness may dominate dielectric loss, so specify HVLP or RA copper on critical signal layers and coordinate with your fab on availability. Glass weave is more than a laminate footnote: tighter, spread styles reduce differential skew and timing uncertainty, especially for long, parallel pairs. And because impedance is geometry and dielectric working together, lock dielectric thicknesses early – not just layer count – so your routing rules and field solves match press-out reality. Thick copper (>2 oz) is invaluable for current but affects etch undercut, annular ring requirements, and via stress; reflect that in DRCs and padstacks.
How to Choose: A Practical Path for First-Time Specifiers
- Define the hardest requirement.
Is it loss/impedance, temperature cycles, bend radius, or cost? Let the hardest constraint drive the material family. For a step-by-step tree, see PCB Materials: How to Choose What Works for Your Design. - Set the loss budget.
Estimate insertion loss from conductor + dielectric + vias. If FR-4’s Df busts budget, jump to low-loss. - Pick copper and glass deliberately.
If you’re over ~10 Gbps differential or doing RF, spec HVLP/RA copper and a spread glass style to reduce skew and loss. - Choose Tg/Td/CTE for assembly reality.
Lead-free and multi-reflow? Go Tg ≥ 170 °C and confirm Z-CTE and Td meet your cycle count. - Lock dielectric thicknesses, not just layer count.
Ask your fab for build sheets that show core/prepreg options with nominal + tolerance. Your impedance tables should match these numbers. Our Stackup Strategy guide (link below) shows how to validate this pre-fab. - Prototype with the production stack-up.
Don’t test on one material and ship another. If you must mix (e.g., FR-4 + RF insert), plan bond plies and drill/plate transitions early.
DFM and purchasing: set yourself up to win
Ask for a controlled stack-up early in the process. Provide impedance targets and copper weights; in return, expect a fab-approved build with Dk/Df sources and dielectric thicknesses. Where possible, specify by performance window instead of single brand—define acceptable ranges for Dk/Df, Tg/Td, Z-CTE, and foil roughness—and allow equivalents to protect supply.
If your design will see multiple reflows or thermal cycles, call out microvia stack limits, fill types, and Z-CTE expectations so reliability is built into the quote. Document the service environment (temperature, humidity, vibration, altitude/vacuum, applicable UL/IPC requirements) and think about panel utilization; small tweaks to outline or copper balance can reduce warp and improve yields.
Common Mistakes New Engineers Make (and how to avoid them)
- Specifying only the layer count. Always pair layer count with dielectric thickness and impedance goals, or you’ll get surprises.
- Assuming FR-4 is all the same. It isn’t. Df and Z-CTE vary widely. Name a class (standard, low-loss) and key properties.
- Ignoring copper roughness. At high frequency, foil texture can dominate loss. Ask for HVLP/RA where it matters.
- Skipping weave considerations. Differential skew from glass weave can ruin lane margins; pick spread glass and stagger routes when possible.
- Prototyping on the wrong stack. Validate performance on the same resin system and foil you plan to ship.